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Designing a Practical Data Filter Cache to Improve Both Energy Efficiency and Performance

Alen Bardizbanyan (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Magnus Själander ; David Whalley ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
ACM Transactions on Architecture and Code Optimization (1544-3566). Vol. 10 (2013), 4, p. 25 pages.
[Artikel, refereegranskad vetenskaplig]

Conventional Data Filter Cache (DFC) designs improve processor energy efficiency, but degrade performance. Furthermore, the single-cycle line transfer suggested in prior studies adversely affects Level-1 Data Cache (L1 DC) area and energy efficiency. We propose a practical DFC that is accessed early in the pipeline and transfers a line over multiple cycles. Our DFC design improves performance and eliminates a substantial fraction of L1 DC accesses for loads, L1 DC tag checks on stores, and data translation lookaside buffer accesses for both loads and stores. Our evaluation shows that the proposed DFC can reduce the data access energy by 42.5% and improve execution time by 4.2%.



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Denna post skapades 2014-01-14. Senast ändrad 2016-09-14.
CPL Pubid: 192300

 

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