CPL - Chalmers Publication Library
| Utbildning | Forskning | Styrkeområden | Om Chalmers | In English In English Ej inloggad.

ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory

Ruben Titos Gil (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Anurag Negi (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Manolis Acacio ; Jose Maria Garcia ; Per Stenström (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
IEEE Transactions on Parallel and Distributed Systems (1045-9219). Vol. 25 (2014), 5, p. 1359-1369.
[Artikel, refereegranskad vetenskaplig]

Transactional contention management policies show considerable variation in relative performance with changing workload characteristics. Consequently, incorporation of fixed-policy Transactional Memory (TM) in general purpose computing systems is suboptimal by design and renders such systems susceptible to pathologies. Of particular concern are Hardware TM (HTM) systems where traditional designs have hardwired policies in silicon. Adaptive HTMs hold promise, but pose major challenges in terms of design and verification costs. In this paper, we present the ZEBRA HTM design, which lays down a simple yet high-performance approach to implement adaptive contention management in hardware. Prior work in this area has associated contention with transactional code blocks. However, we discover that by associating contention with data (cache blocks) accessed by transactional code rather than the code block itself, we achieve a neat match in granularity with that of the cache coherence protocol. This leads to a design that is very simple and yet able to track closely or exceed the performance of the best performing policy for a given workload. ZEBRA, therefore, brings together the inherent benefits of traditional eager HTMs-parallel commits-and lazy HTMs-good optimistic concurrency without deadlock avoidance mechanisms-, combining them into a low-complexity design.

Nyckelord: Multicore architectures; transactional memory; parallel programming; cache coherence protocols

Den här publikationen ingår i följande styrkeområden:

Läs mer om Chalmers styrkeområden  

Denna post skapades 2013-12-11. Senast ändrad 2015-03-23.
CPL Pubid: 188871


Läs direkt!

Länk till annan sajt (kan kräva inloggning)