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Cascode signal driver with low harmonic content

Lars Svensson (Institutionen för datorteknik) ; Sven Mattisson

A method and apparatus for minimizing harmonic content in a digital signal driver circuit are disclosed. A digital input signal applied to an input node generates a corresponding digital output in a circuit with two or more MOS devices in cascode connection with each other. The slew rate of one or more edge transitions associated with the output signal are controlled using one or more parasitic capacitances associated with the fabrication of two or more cascode connected MOS devices. The two or more cascode connected MOS devices may further each have gate electrodes connected to a fixed potential so as to minimize said harmonic content. A control signal may further be applied to each gate electrode to turn off a leakage current path between source and drain electrodes. Harmonics may further be controlled by limiting a conductance between gate electrodes and fixed potentials using an active or passive device.

Denna post skapades 2013-07-09.
CPL Pubid: 179992


Institutioner (Chalmers)

Institutionen för datorteknik (2002-2004)


Data- och informationsvetenskap

Chalmers infrastruktur