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A Mixed-Mode Delay-Locked Loop Architecture

Daniel Eckerbert (Institutionen för datorteknik, Integrerade elektroniksystem) ; Lars Svensson (Institutionen för datorteknik, Integrerade elektroniksystem) ; Per Larsson-Edefors (Institutionen för datorteknik, Integrerade elektroniksystem)
Proceedings of the 21st International Conference on Computer Design (ICCD), San Jose, 13-15 October 2003 (1063-6404). p. 261-263. (2003)
[Konferensbidrag, refereegranskat]

We present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock generation. In contrast to analog DLLs, the proposed architecture allows for clock-gating; moreover circuit simulations indicate that its performance (in terms of maximum frequency, frequency range, and low-speed power dissipation) is superior to that of a previously-reported, purely digital DLL.

Denna post skapades 2006-09-12. Senast ändrad 2016-09-14.
CPL Pubid: 17603


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Institutioner (Chalmers)

Institutionen för datorteknik, Integrerade elektroniksystem (2002-2004)



Chalmers infrastruktur