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A Gate Leakage Reduction Strategy for Future CMOS Circuits

Mindaugas Drazdziulis (Institutionen för datorteknik, Integrerade elektroniksystem) ; Per Larsson-Edefors (Institutionen för datorteknik, Integrerade elektroniksystem)
Proceedings of the 29th European Solid-State Circuits Conference, ESSCIRC 2003, Estoril, 16-18 September 2003 p. 317-320. (2003)
[Konferensbidrag, refereegranskat]

We show that a technique previously introduced for subthreshold leakage reduction can be effectively used to reduce gate leakage power dissipation in future CMOS circuits operating in stand-by mode. The technique gave one order of magnitude gate leakage savings with a certain input pattern for the evaluated two-input NAND gate. Also, we make a detailed analysis of mechanisms causing different direct oxide tunneling currents that will contribute to gate leakage power dissipation in future CMOS circuits.

Denna post skapades 2006-09-12. Senast ändrad 2016-09-14.
CPL Pubid: 17602


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Institutioner (Chalmers)

Institutionen för datorteknik, Integrerade elektroniksystem (2002-2004)



Chalmers infrastruktur

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