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SCIN-Cache: Fast Speculative Versioning in Multithreaded Cores

Anurag Negi (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Ruben Titos Gil (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
ACM Transactions on Architecture and Code Optimization (1544-3566). Vol. 9 (2013), 4,
[Artikel, refereegranskad vetenskaplig]

This article describes cache designs for efficiently supporting speculative techniques like transactional memory on chip multiprocessors with multithreaded cores. On-demand allocation and prompt freeing of speculative cache space in the design reduces the burden on nonspeculative execution. Quick access to both clean and speculative versions of data for multiple contexts provides flexibility and greater design freedom to HTM architects. Performance analysis shows the designs stand up well against other HTM design proposals, with potential performance gains in high contention applications with small transactions.

Nyckelord: Design, Performance, Cache design, speculation support, hardware transactional memory, hardware transactional memory, consistency, processors, coherence

Denna post skapades 2013-03-04.
CPL Pubid: 174344


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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)


Data- och informationsvetenskap

Chalmers infrastruktur



Denna publikation är ett resultat av följande projekt:

High Performance and Embedded Architecture and Compilation (HIPEAC) (EC/FP7/287759)