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Towards a Performance- and Energy-Efficient Data Filter Cache

Alen Bardizbanyan (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Magnus Själander (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; David Whalley ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
Workshop on Optimizations for DSP and Embedded Systems (ODES), Proceedings of International Symposium on Code Generation and Optimization (CGO), Shenzhen, China, Feb. 23-27, p. 21-28. (2013)
[Konferensbidrag, refereegranskat]

As CPU data requests to the level-one (L1) data cache (DC) can represent as much as 25% of an embedded processor's total power dissipation, techniques that decrease L1 DC accesses can significantly enhance processor energy efficiency. Filter caches are known to efficiently decrease the number of accesses to instruction caches. However, due to the irregular access pattern of data accesses, a conventional data filter cache (DFC) has a high miss rate, which degrades processor performance. We propose to integrate a DFC with a fast address calculation technique to significantly reduce the impact of misses and to improve performance by enabling one-cycle loads. Furthermore, we show that DFC stalls can be eliminated even after unsuccessful fast address calculations, by simultaneously accessing the DFC and L1 DC on the following cycle. We quantitatively evaluate different DFC configurations, with and without the fast address calculation technique, using different write allocation policies, and qualitatively describe their impact on energy efficiency. The proposed design provides an efficient DFC that yields both energy and performance improvements.

Nyckelord: Data cache; Energy; Execution time; Memory hierarchy; Speculation



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Denna post skapades 2013-02-25. Senast ändrad 2016-09-14.
CPL Pubid: 174065

 

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