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FASTER: Facilitating analysis and synthesis technologies for effective reconfiguration

D. Pnevmatikatos ; T. Becker ; A. Brokalakis ; K. Bruneel ; Georgi N. Gaydadjiev (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; W. Luk ; K. Papadimitriou ; I. Papaefstathiou ; O. Pell ; C. Pilato ; M. Robart ; M. D. Santambrogio ; D. Sciuto ; D. Stroobandt ; T. Todman
15th Euromicro Conference on Digital System Design, DSD 2012; Cesme, Izmir; Turkey; 5 September 2012 through 8 September 2012 p. 234-241. (2012)
[Konferensbidrag, refereegranskat]

The FASTER project aims to ease the definition, implementation and use of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving better performance and extending product functionality and lifetime via the addition of new features that work at hardware speed. This is a clear advantage over the more straightforward software component adaptivity. However, designing a changing hardware system is both challenging and time consuming. The FASTER project will facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily specify, analyse, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. To better adapt to different application requirements, the tool-chain will support both region-based and micro-reconfiguration and provide a flexible run-time system that will efficiently manage the reconfigurable resources. We will use applications from the embedded, high performance computing, and desktop domains to demonstrate the potential benefits of the FASTER tools on metrics such as performance, power consumption and total ownership cost.

Nyckelord: partial reconfiguration, reconfigurable computing, relocation, run-time reconfiguration, run-time system, tools for reconfiguration

Article number 6386896

Denna post skapades 2013-02-25. Senast ändrad 2016-08-18.
CPL Pubid: 174055


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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)


Data- och informationsvetenskap

Chalmers infrastruktur



Denna publikation är ett resultat av följande projekt:

Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration (FASTER) (EC/FP7/287804)