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A 3.5GHz 32mW 150nm Multiphase Clock Generator for High-Performance Microprocessors

A. Alvandpour ; R.K. Krishnamurthy ; Daniel Eckerbert (Institutionen för datorteknik) ; S. Apperson ; B. Bloechel ; S. Borkar
Digest of Technical Papers. IEEE International Solid-State Circuits Conference, 9-13 February 2003 (0193-6530). (2003)
[Konferensbidrag, refereegranskat]

A 3.5GHz 8-phase all-digital clock generator is fabricated in 150nm CMOS to achieve scalable 1.7x frequency-range and 9ps end-to-end time resolution measured at 1.6V and 110°C. A closed-to-open loop control scheme enables 32mW open-loop power consumption, 300μW at clock gate-off, zero-cycle response during clock re-enable, and <4% static phase error.

Denna post skapades 2013-02-20.
CPL Pubid: 173896


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Institutionen för datorteknik (2002-2004)



Chalmers infrastruktur