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Improvement of energy-efficiency in off-chip caches by selective prefetching

Jonas Jalminger (Institutionen för datorteknik) ; Per Stenström (Institutionen för datorteknik)
Microprocessors and microsystems (0141-9331). Vol. 26 (2002), 3, p. 107-121.
[Artikel, refereegranskad vetenskaplig]

The line size/performance trade-offs in off-chip second-level caches in light of energy-efficiency are revisited. Based on a mix of applications representing server and mobile computer system usage, we show that while the large line sizes (128 bytes) typically used maximize performance, they result in a high power dissipation owing to the limited exploitation of spatial locality. In contrast, small blocks (32 bytes) are found to cut the energy-delay by more than a factor of 2 with only a moderate performance loss of less than 25%. As a remedy, prefetching, if applied selectively, is shown to avoid the performance losses of small blocks, yet keeping power consumption low.

Nyckelord: caches, energy-efficiency, energy-delay, performance evaluation, prefetching

Denna post skapades 2013-02-14.
CPL Pubid: 173621


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Institutioner (Chalmers)

Institutionen för datorteknik (2002-2004)



Chalmers infrastruktur