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Modelling and Characterisation of Terahertz Planar Schottky Diodes

Aik Yean Tang (Institutionen för mikroteknologi och nanovetenskap, Terahertz- och millimetervågsteknik ; GigaHertz Centrum)
Göteborg : Chalmers University of Technology, 2013. ISBN: 978-91-7385-820-5.
[Doktorsavhandling]

This thesis deals with the modelling and characterisation of THz planar Schottky diodes, focusing on analyses of geometry-dependent electrical parasitics and the thermal management of the diode chip. Moving towards higher operating frequencies, the diode performance degrades due to high frequency losses, parasitic couplings and self-heating effects. For geometry-dependent electrical parasitics analyses, the diode equivalent circuit parameters can be extracted from the measured or 3-D EM calculated S-parameters. For planar Schottky diodes, the available parameter extraction methods are typically based on an optimisation approach. In this work, a parameter extraction method based on an analytical approach is proposed. The proposed method allows for a fast and more reliable diode model extraction. In this work, the high frequency diode parasitic esistance model is extended to include the eddy current and a mixture of skin and proximity effects. Due to the eddy current and proximity effects, the upper boundary of the buffer layer thickness is approximately one skin depth at the operating frequency, whereas the lower boundary is limited by the spreading resistance at DC. Reactive energies stored in the parasitic capacitances and inductances cause an inherent limitation in the power coupling bandwidth to the intrinsic diode junction. The influence of diode geometry on fundamental power coupling bandwidth limitation is analysed using the Bode-Fano criterion. The result shows a trade-off between the parasitic capacitance and finger inductance,determined by the pad-to-pad distance, in optimising the diode geometry for a wide band diode matching. A systematic thermal analysis of a 200 GHz multiplier chip developed by JPL is performed. The result shows that the chip thermal resistance is in the order of 10^3 K/W, whereas the overall thermal settling time is more than tens of milliseconds. The simulation result is verified through thermal imaging using infrared microscopy. Taking the thermal analysis a step further, a self-consistent electrothermal model for the multiplier chip is proposed. Compared to the circuit analysis without the thermal model, analysis with the electrothermal model shows a better agreement with the measured result, e.g., an error reduction from ~13% to ~4% between the simulated and measured maximum output power, by including the thermal effect.



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Denna post skapades 2013-02-05. Senast ändrad 2013-09-25.
CPL Pubid: 172943