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Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory

Ruben Titos Gil (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; M. E. Acacio ; J. M. Garcia
IEEE Transactions on Parallel and Distributed Systems (1045-9219). Vol. 24 (2013), 1, p. 59-71.
[Artikel, refereegranskad vetenskaplig]

The efficient management of conflicts among concurrent transactions constitutes a key aspect that hardware transactional memory (HTM) systems must achieve. Scalable HTM proposals so far inherit the cache-based style of conflict detection typically found in bus-based systems, largely unaware of the interactions between transactions and directory coherence. In this paper, we demonstrate that the traditional approach of detecting conflicts at the private cache levels is inefficient when used in the context of a directory protocol. We find that the use of the directory as a mere router of coherence requests restricts the throughput of conflict detection, and show how it becomes a bottleneck under high contention. This paper proposes a scheme for conflict detection that decouples conflict detection from cache coherence in order to overcome pathological situations that degrade the performance of an eager HTM system. Our scheme places bookkeeping metadata at the directory, introducing it as a separate hardware module that leaves the coherence protocol unmodified. In comparison to a state-of-the-art eager HTM system, our design handles contention more efficiently, minimizes the performance degradation of false positives for signatures of similar hardware cost, and reduces the network traffic generated.

Nyckelord: Parallel programming, multicore architectures, cache coherence, protocols, transactional memory, conflict detection, consistency, signatures, coherence



Denna post skapades 2013-02-04.
CPL Pubid: 172867

 

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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Datorteknik

Chalmers infrastruktur