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Transactional prefetching: Narrowing the window of contention in hardware transactional memory

Anurag Negi (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; A. Armejach ; A. Cristal ; O.S. Unsal ; Per Stenström (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
21st International Conference on Parallel Architectures and Compilation Techniques, PACT 2012. Minneapolis, MN, 19 - 23 September 2012 (1089-795X). p. 181-190. (2012)
[Konferensbidrag, refereegranskat]

Memory access latency is the primary performance bottle-neck in modern computer systems. Prefetching data before it is needed by a processing core allows substantial performance gains by overlapping significant portions of memory latency with useful work. Prior work has investigated this technique and measured potential benefits in a variety of scenarios. However, its use in speeding up Hardware Transactional Memory (HTM) has remained hitherto unexplored. In several HTM designs transactions invalidate speculatively updated cache lines when they abort. Such cache lines tend to have high locality and are likely to be accessed again when the transaction re-executes. Coarse grained transactions that update several cache lines are particularly susceptible to performance degradation even under moderate contention. However, such transactions show strong locality of reference, especially when contention is high. Prefetching cache lines with high locality can, therefore, improve overall concurrency by speeding up transactions and, thereby, narrowing the window of time in which such transactions persist and can cause contention. Such transactions are important since they are likely to form a common TM use-case. We note that traditional prefetch techniques may not be able to track such lines adequately or issue prefetches quickly enough. This paper investigates the use of prefetching in HTMs, proposing a simple design to identify and request prefetch candidates, and measures performance gains to be had for several representative TM workloads.

Nyckelord: Hardware transactional memory, Multicores, Prefetching

Denna post skapades 2012-11-14. Senast ändrad 2016-06-28.
CPL Pubid: 166061


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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)


Data- och informationsvetenskap

Chalmers infrastruktur