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Understanding the Performance of Concurrent Data Structures on Graphics Processors

Daniel Cederman (Institutionen för data- och informationsteknik, Nätverk och system, Datakommunikation och distribuerade system (Chalmers)) ; Bapi Chatterjee (Institutionen för data- och informationsteknik, Nätverk och system, Datakommunikation och distribuerade system (Chalmers)) ; Philippas Tsigas (Institutionen för data- och informationsteknik, Nätverk och system, Datakommunikation och distribuerade system (Chalmers))
Lecture Notes in Computer Science, Proceedings of the 18th International Conference on Parallel Processing - Euro-Par'12 (0302-9743). Vol. 7484/2012 (2012), p. 883-894.
[Konferensbidrag, refereegranskat]

In this paper we revisit the design of concurrent data structures -- specifically queues -- and examine their performance portability with regard to the move from conventional CPUs to graphics processors. We have looked at both lock-based and lock-free algorithms and have, for comparison, implemented and optimized the same algorithms on both graphics processors and multi-core CPUs. Particular interest has been paid to study the difference between the old Tesla and the new Fermi and Kepler architectures in this context. We provide a comprehensive evaluation and analysis of our implementations on all examined platforms. Our results indicate that the queues are in general performance portable, but that platform specific optimizations are possible to increase performance. The Fermi and Kepler GPUs, with optimized atomic operations, are observed to provide excellent scalability for both lock-based and lock-free queues.

Nyckelord: gpgpu, data structures, queues, cuda, spsc, mpmc, performance portability



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Denna post skapades 2012-09-02.
CPL Pubid: 162779

 

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