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Influence of interlayer properties on the characteristics of high-k gate stacks

Olof Engström (Institutionen för mikroteknologi och nanovetenskap, Terahertz- och millimetervågsteknik ) ; I. Z. Mitrovic ; S. Hall
Solid-State Electronics (0038-1101). Vol. 75 (2012), p. 63-68.
[Artikel, refereegranskad vetenskaplig]

The significance of interface sharpness between interlayers and high-k oxides for the properties of transistor gate-stacks has been investigated. Energy band variation in the oxide is calculated by using literature data for the HfO2/SiO2 interface, assuming two different cases for the interface plane: flat with a gradual depth variation of k-value and rough with an abrupt change of k. We demonstrate that the capacitive properties are similar, whereas tunneling properties considerably differ between the two cases. Furthermore, depth distributions of tunneling effective mass and dielectric constant have a substantial influence on the probability for charge carrier tunneling through the oxide stack and for the determination of capacitance equivalent oxide thickness (CET).

Nyckelord: MOS, High-k dielectric, Interlayer, C-V, Tunneling probability, chemical-vapor-deposition, interface, dielectrics, films, oxide, hfo2



Denna post skapades 2012-08-23.
CPL Pubid: 162498

 

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