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Data-Width-Driven Power Gating of Integer Arithmetic Circuits

Tung Hoang-Thanh (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, 19-21 August 2012 Article number 6296479, p. 237-242. (2012)
[Konferensbidrag, refereegranskat]

When performing narrow-width computations, power gating of unused arithmetic circuit portions can significantly reduce leakage power. We deploy coarse-grain power gating in 32-bit integer arithmetic circuits that frequently will operate on narrow-width data. Our contributions include a design framework that automatically implements coarse-grain power-gated arithmetic circuits considering a narrow-width input data mode, and an analysis of the impact of circuit architecture on the efficiency of this data-width-driven power gating scheme. As an example, with a performance penalty of 6.7%, coarse-grain power gating of a 45-nm 32-bit multiplier is demonstrated to yield an 11.6x static leakage energy reduction per 8x8-bit operation.



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Denna post skapades 2012-07-09. Senast ändrad 2016-09-14.
CPL Pubid: 160250

 

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