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Design principles for synthesizable processor cores

P. Schleuniger ; Sally A McKee (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; S. Karlsson
Lecture Notes in Computer Science. 25th International Conference on Architecture of Computing Systems, Munich, 28 February - 2 March 2012 (0302-9743). Vol. 7179 (2012), p. 111-122.
[Konferensbidrag, refereegranskat]

As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration.

Nyckelord: FPGA, pipelining, predication, synthesizable processor core, Design Principles, Embedded computing, FPGA architectures, FPGA implementations, Pipeline stall, Processor architectures, Processor cores, System clock, Architecture, Benchmarking, Computer architecture, Embedded software, Field programmable gate arrays (FPGA), Pipe linings, Pipeline processing systems

Denna post skapades 2012-07-06. Senast ändrad 2016-03-22.
CPL Pubid: 160182


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Institutionen för data- och informationsteknik, Datorteknik (Chalmers)


Data- och informationsvetenskap

Chalmers infrastruktur