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Feasibility Study of FPGA-Based Equalizer for 112-Gbit/s Optical Fiber Receivers

Fredrik Toft (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Niclas Rousk (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Jonas Mårtensson ; Marco Forzati ; Bengt-Erik Olsson ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, 20-23 May 2012 (0271-4302). p. 3234-3237. (2012)
[Konferensbidrag, refereegranskat]

With ever increasing demands on spectral efficiency, complex modulation schemes are being introduced in fiber communication. However, these schemes are challenging to implement as they drastically increase the computational burden at the fiber receiver’s end. We perform a feasibility study of implementing a 16-QAM 112-Gbit/s decision directed equalizer on a state-of-the-art FPGA platform. An FPGA offers the reconfigurability needed to allow for modulation scheme updates, however, its clock rate is limited. For this purpose, we introduce a new phase correction technique to significantly relax the delay requirement on the critical phase-recovery feedback loop.

Nyckelord: Clock rate, Complex modulation, Computational burden, Decision-directed, Feasibility studies, Feed-back loop, In-fiber, Modulation schemes, Phase corrections, Reconfigurability, Spectral efficiencies

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Denna post skapades 2012-05-08. Senast ändrad 2016-09-14.
CPL Pubid: 157411


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