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Classification and Elimination of Conflicts in Hardware-Transactional Memory Systems

M.M. Waliullah ; Per Stenström (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
23rd International Conference on Computer Architecture and High Performance Computing (SBAC-PAD 2011) (15506533). p. 96-103 . (2011)
[Konferensbidrag, refereegranskat]

This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper first proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance is improved substantially. © 2011 IEEE.

Nyckelord: Contamination Misses; Intermediate Checkpointing; Manycore; Transactional Memory

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Denna post skapades 2011-09-17. Senast ändrad 2016-07-21.
CPL Pubid: 146307


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