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Power Gating Multiplier of Embedded Processor Datapath

Tung Hoang-Thanh (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Vineeth Saseendran (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Donatas Siaudinis (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
Proceedings of 7th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Madonna di Campiglio, Trento; 3 July 2011 through 7 July 2011 p. 41-44. (2011)
[Konferensbidrag, refereegranskat]

Leakage power is an important concern in modern electronic designs. To efficiently employ power gating for leakage reduction in embedded processors, the architecture must provide a clear-cut software support for power gating and the power-gated unit must have significant idle times during the execution of the applications. We introduce power gating of individual datapath units for the embedded architecture of FlexCore, to evaluate if leakage reductions in temporarily idle units can reduce the overall power dissipation of compute-intensive applications. Post-layout multi-corner simulations for a 65-nm FlexCore datapath implementation demonstrate that power gating of the multiplier unit yields overall datapath energy savings, up to 14%, for two EEMBC benchmarks.



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Denna post skapades 2011-07-24. Senast ändrad 2016-09-14.
CPL Pubid: 143597

 

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