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Reconfigurable Instruction Decoding for a Wide-Control-Word Processor

Alen Bardizbanyan (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Magnus Själander (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
Proceedings of Reconfigurable Architectures Workshop (RAW), IEEE International Parallel & Distributed Processing Symposium (IPDPS) p. 322-325 . (2011)
[Konferensbidrag, refereegranskat]

Fine-grained control through the use of a wide control word can lead to high instruction-level parallelism, but unless compressed the words require a large memory footprint. A reconfigurable fixed-length decoding scheme can be created by taking advantage of the fact that an application only uses a subset of the datapath for its execution. We present the first complete implementation of the FlexCore processor, integrating a wide-control-word datapath with a run-time reconfigurable instruction decompressor. Our evaluation, using three different EEMBC benchmarks, shows that it is possible to reach up to 35% speedup compared to a five-stage pipelined MIPS processor, assuming the same datapath units. In addition, our VLSI implementations show that this FlexCore processor offers up to 24% higher energy efficiency than the MIPS reference processor.

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Denna post skapades 2011-05-18. Senast ändrad 2016-09-14.
CPL Pubid: 140771


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