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Characterization and Exploitation of Narrow-Width Loads:The Narrow-Width Cache Approach

Mafijul Islam (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Per Stenström (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
IEEE/ACM International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES 2010) p. 227-236. (2010)
[Konferensbidrag, refereegranskat]

This paper exploits small-value locality to accelerate the execution of memory instructions. We find that narrow-width loads (NWLDs) — loads with small-value operands of 8 bits or less — comprise 26% of all executed loads across 40 applications of the SPEC benchmark suites. We establish that the frequency of NWLDs are almost independent of compiler and input data. We introduce narrow-width caches (NWC) to cache small-value memory words. NWCs provide a significant speedup for several memory-intensive applications with a negligible chip-area overhead. NWCs also reduce the overall energy dissipation and memory traffic.

Nyckelord: Small Value Locality, Narrow-Width Load, Narrow-Width Cache



Denna post skapades 2010-07-02. Senast ändrad 2016-07-21.
CPL Pubid: 123628

 

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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Datorteknik

Chalmers infrastruktur

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