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Design and Fabrication of 0/1-Level RF-Via Interconnect for RF-MEMS Packaging Applications

L. H. Hsu ; W. C. Wu ; E. Y. Chang ; Herbert Zirath (Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik) ; Y. C. Wu ; C. T. Wang ; C. T. Lee
Ieee Transactions on Advanced Packaging (1521-3323). Vol. 33 (2010), 1, p. 30-36.
[Artikel, refereegranskad vetenskaplig]

This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.

Nyckelord: Fabrication, interconnections, microelectromechanical devices, microwave technology, packaging, flip-chip interconnects, cpw, ghz

Denna post skapades 2010-06-24. Senast ändrad 2017-03-21.
CPL Pubid: 123389


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Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik


Elektroteknik och elektronik

Chalmers infrastruktur