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Parameter Extraction and Geometry Optimisation of Planar Schottky Diodes

Aik Yean Tang (Institutionen för mikroteknologi och nanovetenskap, Fysikalisk elektronik) ; Peter Sobis (Institutionen för mikroteknologi och nanovetenskap, Fysikalisk elektronik) ; Vladimir Drakinskiy (Institutionen för mikroteknologi och nanovetenskap, Fysikalisk elektronik) ; Huan Zhao (Institutionen för mikroteknologi och nanovetenskap, Fysikalisk elektronik) ; Jan Stake (Institutionen för mikroteknologi och nanovetenskap, Fysikalisk elektronik)
21st International Symposium on Space Terahertz Technology 2010, ISSTT 2010; Oxford; United Kingdom; 23 March 2010 through 25 March 2010 (2010)
[Konferensbidrag, refereegranskat]

The continuous interests in terahertz (300 GHz to 10 THz) applications have generated technology pressure in the search of reliable, room temperature operational and compact sources and detectors. Various terahertz sources such as optically pumped lasers, backward wave oscillators, and direct multiplied sources have been explored [1]. For direct multiplied sources, the GaAs-based Schottky diode is one of the most critical devices in heterodyne receivers operating at millimetre and sub-millimetre wavelengths. The importance of Schottky diode could be seen from the meticulous efforts in the diode technology advancement. This includes the evolvement of the whisker contact to the surface channel planar diode technology [2] as well as the circuit integration of the discrete Schottky diodes. For high frequency applications, the performance of a GaAs Schottky diode is limited by the parasitic elements [3] and the losses due to skin effects [4]. Thus, systematic studies of the Schottky diode parasitic elements and high frequency losses are very crucial in meeting the design goals. In the search of optimised diode performance, several studies on diode modelling have been performed [5], [6]. In this paper, we present a systematic method to estimate the diode geometry dependent parasitic elements and skin effect losses for diodes operating up to 400 GHz. Different diode geometries, such as padto- pad distance, buffer layer thickness and semi-insulating etch depth have been investigated. The equivalent circuit based method as in [7] has been used, where the parasitic elements are extracted through the least square error fitting of the S-parameters simulated in Ansoft HFSS simulator to the lumped equivalent circuit. Simulations are performed with the semi-insulating substrate of 3 μm (for the case of integrated diode on the membrane) and 10 μm (for the case of discrete diode). In addition, high frequency losses are investigated with the similar method, by using lossy conductors and adding a frequency dependent resistor in the lumped equivalent circuit. Analysis of the simulation and measurement results will be presented.

Denna post skapades 2010-03-30. Senast ändrad 2016-05-11.
CPL Pubid: 118852


Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap, Fysikalisk elektronik (2007-2010)


Informations- och kommunikationsteknik
Nanovetenskap och nanoteknik

Chalmers infrastruktur