CPL - Chalmers Publication Library
| Utbildning | Forskning | Styrkeområden | Om Chalmers | In English In English Ej inloggad.

Towards a Software Transactional Memory for CUDA

Daniel Cederman (Institutionen för data- och informationsteknik, Nätverk och system, Datakommunikation och distribuerade system (Chalmers)) ; Muhammad Tayyab Chaudhry ; Philippas Tsigas (Institutionen för data- och informationsteknik, Nätverk och system, Datakommunikation och distribuerade system (Chalmers))
MCC09 Proceedings (2009)
[Konferensbidrag, refereegranskat]

The introduction of CUDA, NVIDIA's system for general purpose computing on their many-core graphics processor system, and the general shift in the industry towards parallelism, has created a demand for ease of parallelization. Software transactional memory (STM) simplifies development of concurrent code by allowing the programmer to mark sections of code to be executed atomically. The STM will then guarantee that other processes will see either none or all of the writes done in in that section. In contrast to using locks, STM:s are easy to compose and does not suffer from deadlocks. An STM can thus be seen as a concurrency control mechanism. In this paper we report on our work towards implementing a simple software transactional memory in CUDA.



Denna post skapades 2010-01-29.
CPL Pubid: 111214