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Compiler-Based Approaches to Reduce Memory. Access Penalties in Cache Coherent Multiprocessors

Jonas Skeppstedt (Institutionen för datorteknik)
Göteborg : Chalmers University of Technology, 1997. ISBN: 91-7197-452-0.

To reduce the average time needed to perform a read or a write access in a multiprocessor, a cache is associated with each processor. A hardware mechanism is used to ensure that the replicated cache copies are consistent. This mechanism employs a protocol which controls when a node may read and/or write a shared data item. The time a processor is waiting for actions of the protocol to be performed, called the memory access penalty, limits the performance that can be achieved.

Nyckelord: cache coherent multiprocessors, memory access penalty, compiler analysis, hardware support, performance evaluation

Denna post skapades 2006-08-25. Senast ändrad 2013-09-25.
CPL Pubid: 1085


Institutioner (Chalmers)

Institutionen för datorteknik (1985-2001)


Information Technology

Chalmers infrastruktur

Ingår i serie

Technical report - School of Electrical and Computer Engineering, Chalmers University of Technology, Göteborg, Sweden 305

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie 1280