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3D chip stacking using planarized carbon nanotubes as through-silicon-vias

Kjell Jeppson (Institutionen för mikroteknologi och nanovetenskap, Fysikalisk elektronik) ; Teng Wang (Institutionen för mikroteknologi och nanovetenskap, Bionanosystem) ; Johan Liu (Institutionen för mikroteknologi och nanovetenskap, Bionanosystem) ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
Swedish System on Chip Conference (2009)
[Konferensbidrag, övrigt]

Future miniaturization of advanced electronic systems will require 3D chip-to-chip stacking of high performance processor chips. Such systems raise a number of questions concerning power distribution and thermal management issues. Efficient through-silicon-via (TSV) technology and new thermal interface materials will be required for such systems to be successful. Carbon nanotubes (CNT) have been suggested as a candidate material with good mechanical properties, and good thermal and electrical conductivities superior to those of copper TSVs. In this paper we will describe our efforts on producing through-silicon-vias based on carbon nanotube bundles grown from the bottom of 150 m deep silicon vias with 50*50 µm openings. The resistances of such CNT vias have been electrically measured and found to be about 2.0 kΩ, a result very close to previously reported values. However, these values are orders of magnitude too high for practical use and not at all close to values reported from measurements on short carbon nanotubes. New processes are suggested too improve growth of long CNTs.


Arild, May 4-5, 2009



Denna post skapades 2009-12-03. Senast ändrad 2016-09-14.
CPL Pubid: 102697

 

Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap, Fysikalisk elektronik (2007-2010)
Institutionen för mikroteknologi och nanovetenskap, Bionanosystem (2007-2015)
Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Elektroteknik och elektronik

Chalmers infrastruktur