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Digital Predistortion Linearization of High Efficiency Transmitters

Haiying Cao (Institutionen för mikroteknologi och nanovetenskap ; GigaHertz Centrum)
Göteborg : Chalmers University of Technology, 2009. - 112 s.
[Licentiatavhandling]

High efficiency and good linearity are two important characteristics of transmitters in future wireless communication systems. However, there is usually a trade-off: when high efficiency is achieved, linearity is degraded and nonlinear distortion occurs. This thesis investigates digital predistortion techniques to suppress nonlinear distortion and memory effects in transmitters, therefore improving the linearity. The power amplifier and RF modulator are the two main sources of distortion in transmitters. First, based on the traditional, widely used Volterra series, a dual-input Volterra series is presented to compensate for the I/Q imbalance which is the main distortion in RF modulators. Further on, a more wideband case is studied for the I/Q imbalance compensation, which can present stronger memory effects in the modulator. In order to deal with this situation, two modified, complexity reduced behavioral models are introduced. Later, joint distortion compensation of the modulator and the power amplifier are investigated. The experimental results show that the dual-input models can effectively compensate for the I/Q imbalance and also the distortion from the power amplifier, especially when there exists strong nonlinear I/Q imbalance in the transmitter. In order to improve the average efficiency in the transmitter while maintaining low distortion, a varactor-based dynamic load modulation architecture is studied in the second part of the thesis. This dual-input architecture has an extra degree of freedom for behavioral modeling and the two input signals need to be controlled carefully together to achieve maximum efficiency. For this purpose, a dual-input/single output quasi-static inverse model is first used to construct the input signals. Due to different time delays that exist in the two signal paths, a time alignment algorithm is then introduced to estimate the relative time delay. Finally, a dedicated linearization scheme is used to improve the linearity. The experiment is performed using a transmitter demonstrator based on a 1 GHz LDMOS high power amplifier. A 53% power added efficiency with -43 dBc adjacent channel leakage ratio is obtained. These results represent state-of-the-art for dynamic load modulation transmitters and are equivalent to those obtained with other competing methods.



Denna post skapades 2009-10-29. Senast ändrad 2010-06-29.
CPL Pubid: 101024

 

Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap
GigaHertz Centrum

Ämnesområden

Elektroteknik

Chalmers infrastruktur

Examination

Datum: 2009-12-03
Tid: 15:15
Lokal: Kollektorn, MC2
Opponent: Magnus Isaksson, Högskolan i Gävle

Ingår i serie

Technical report MC2 - Department of Microtechnology and Nanoscience, Chalmers University of Technology 157