CPL - Chalmers Publication Library
| Utbildning | Forskning | Styrkeområden | Om Chalmers | In English In English Ej inloggad.

New Design of a RSFQ Parallel Multiply-Accumulate Unit

Irina Kataeva (Institutionen för mikroteknologi och nanovetenskap, Fasta tillståndets elektronik) ; Henrik Engseth (Institutionen för mikroteknologi och nanovetenskap, Fasta tillståndets elektronik) ; Anna Kidiyarova-Shevchenko (Institutionen för mikroteknologi och nanovetenskap, Fasta tillståndets elektronik)
Superconducting Science and technology Vol. 19 (2006), p. S381-S386.
[Artikel, refereegranskad vetenskaplig]

The Multiply-Accumulate Unit (MAC) is a central component of a Successive Interference Canceller, an advanced receiver for W-CDMA base stations. A 4*4 two's complement fixed point RSFQ MAC with rounding to 5 bits has been simulated using VHDL and maximum performance is equal to 24 GMACS (giga multiple-accumulates per second). The clock distribution network has been re-designed from a linear ripple to a binary tree network in order to eliminate data dependence of the clock propagation speed and reduce number of Josephson junctions in clock lines. The 4*4 bits MAC has been designed for the HYPRES 4.5 kA/cm^2 process and its components have been experimentally tested at low frequency: the 5 bit combiner, using an exhaustive test pattern, had margins on DC bias voltage of +-18% and the 4*4 parallel multiplier had margins equal to +-2%.

Nyckelord: RSFQ, VHDL, MAC



Denna post skapades 2007-01-15.
CPL Pubid: 10061

 

Läs direkt!


Länk till annan sajt (kan kräva inloggning)


Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap, Fasta tillståndets elektronik (2003-2006)

Ämnesområden

Övrig elektroteknik, elektronik och fotonik
Övrig teknisk fysik

Chalmers infrastruktur

Relaterade publikationer

Denna publikation ingår i:


Experimental Verification of Superconductor Digital Circuits


Superconductor Digital Signal Processor


Experimental Verification of Superconductor Digital Circuits